Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
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68 results for Bruce Doris
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Extreme scaling with ultra-thin Si channel MOSFETs
- Bruce Doris
- Meikei Ieong
- et al.
- 2002
- IEDM 2002
Examination of hole mobility in ultra-thin body SOI MOSFETs
- Zhibin Ren
- Paul M. Solomon
- et al.
- 2002
- IEDM 2002
Hole transport in strained and relaxed sige channel extremely thin SOI MOSFETs
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2013
- IEEE Electron Device Letters
Scalability of extremely thin SOI (ETSOI) MOSFETs to sub-20-nm gate length
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2012
- IEEE Electron Device Letters
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- Kingsuk Maitra
- Ali Khakifirooz
- et al.
- 2011
- IEEE Electron Device Letters
High-performance partially depleted SOI PFETs with in situ doped sige raised source/drain and implant-free extension
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2011
- IEEE Electron Device Letters
Silicon device scaling to the sub-10-nm regime
- Meikei Ieong
- Bruce Doris
- et al.
- 2004
- Science
Mapping of Electrostatic Potential in Deep Submicron CMOS Devices by Electron Holography
- M. Gribelyuk
- M.R. McCartney
- et al.
- 2002
- Physical Review Letters