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(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineeringB. YangA. Waiteet al.2007IEDM 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithographyS. NarasimhaK. Onishiet al.2006IEDM 2006
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengthsD. SinghJ. Sleightet al.2005IEDM 2005
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Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETsH. NayfehD. Singhet al.2006IEEE Electron Device Letters
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copperB. GreeneQ. Lianget al.2009VLSI Technology 2009
Effect of ion implantation and anneals on fully-strained SiC and SiC:P films using multiple characterization techniquesA. MadanJ. Liet al.2008ECS Meeting 2008
Recent progress and challenges in enabling embedded Si:C technologyB. YangZ. Renet al.2008ECS Meeting 2008
On implementation of embedded Phosphorus-doped SiC stressors in SOI nMOSFETsZhibin RenG. Peiet al.2008VLSI Technology 2008