FinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
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27 results for Omer H. Dokumaci
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008
Simulation study of multiple FIN FinFET design for 32nm technology node and beyond
- Xinlin Wang
- Andres Bryant
- et al.
- 2007
- SISPAD 2007
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
Ultra-thin SOI CMOS using laser spike anneal
- Zhibin Ren
- J. Sleight
- et al.
- 2006
- VLSI-TSA 2006
Silicon CMOS devices beyond scaling
- Wilfried Haensch
- Edward J. Nowak
- et al.
- 2006
- IBM J. Res. Dev
Optimizing CMOS technology for maximum performance
- David J. Frank
- Wilfried Haensch
- et al.
- 2006
- IBM J. Res. Dev
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005