Challenges and opportunities for high performance 32 nm CMOS technology

Abstract

Starting with the 45 nm node, a tradeoff between performance and density exists that will become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch" approach is demonstrated to show up to a 15% improvement over conventional layout in ring oscillators. The lower parasitics of SOI provide an additional degree of freedom allowing relaxed pitch designs to enhance performance in critical paths. Simpler device isolation in SOI is also shown to be very beneficial in this generation leading to an improved cost/performance tradeoff compared to previous generations.