Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
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5 results for M. Steigerwalt
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate
- Jin Cai
- Mahender Kumar
- et al.
- 2003
- BCTM 2003
Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
- Jin Cai
- A. Ajmera
- et al.
- 2002
- VLSI Technology 2002