Design of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
Publications
Date
Featured collections
Popular topics
13 results for A. Ajmera
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications
- D.A. Buchanan
- E. Gusev
- et al.
- 2000
- IEDM 2000
Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation
- E. Leobandung
- M. Sherony
- et al.
- 1998
- IEDM 1998
7.9/5.5 psec room/low temperature SOI CMOS
- F. Assaderaghi
- W. Rausch
- et al.
- 1997
- IEDM 1997
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
- Jin Cai
- A. Ajmera
- et al.
- 2002
- VLSI Technology 2002