Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
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13 results for A. Ajmera
Design of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
- Jin Cai
- A. Ajmera
- et al.
- 2002
- VLSI Technology 2002
Ultrathin high-K gate stacks for advanced CMOS devices
- E. Gusev
- D.A. Buchanan
- et al.
- 2001
- Technical Digest - International Electron Devices Meeting
80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications
- D.A. Buchanan
- E. Gusev
- et al.
- 2000
- IEDM 2000
0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Device and circuit design issues in SOI technology
- G. Shahidi
- A. Ajmera
- et al.
- 1999
- CICC 1999