0.22 μm CMOS-SOI technology with a Cu BEOL

Abstract

A 0.22 μm CMOS on SOI technology, using a non-fully depleted device, is developed. This technology uses the same gate lithography and metalization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furthermore, it offers the complete device and circuit elements used in bulk CMOS (low VT device, ESD diode, and decoupling C). This technology was applied to a 64b RISC processor.