Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
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31 results for Stephen Kosonocky
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
Structured and tuned array generation (STAG) for high-performance random logic
- Matthew M. Ziegler
- Gary S. Ditlow
- et al.
- 2007
- GLSVLSI 2007
Multi-dimensional circuit and micro-architecture level optimization
- Qi Zhenyu
- Matthew Ziegler
- et al.
- 2007
- ISQED 2007
A 3-transistor DRAM cell with gated diode for enhanced speed and retention time
- Wing K. Luk
- Jin Cai
- et al.
- 2006
- VLSI Circuits 2006
The design and implementation of a low-overhead supply-gated SRAM
- J.B. Kuang
- Hung Ngo
- et al.
- 2006
- ESSCIRC 2006
Scalability options for future SRAM memories
- Stephen V. Kosonocky
- Azeez Bhavnagarwala
- et al.
- 2006
- ICSICT 2006
A synchronous interface for SoCs with multiple clock domains
- Visvesh Sathe
- Conrad Ziesler
- et al.
- 2004
- SOCC 2004
A transregional CMOS SRAM with single, logic V DD and dynamic power rails
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2004
- VLSI Circuits 2004
Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004