Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
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31 results for Stephen Kosonocky
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
- Phillip Chin
- Charles A. Zukowski
- et al.
- 2005
- Integration, the VLSI Journal
A synchronous interface for SoCs with multiple clock domains
- Visvesh Sathe
- Conrad Ziesler
- et al.
- 2004
- SOCC 2004
A transregional CMOS SRAM with single, logic V DD and dynamic power rails
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2004
- VLSI Circuits 2004
Experimental measurement of a novel power gating structure with intermediate power saving mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004
Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004
Characterization of logic circuit techniques for high leakage CMOS technologies
- Phillip Chin
- Charles A. Zukowski
- et al.
- 2004
- GLSVLSI 2004
Minimizing inductive noise in system-on-a-chip with multiple power gating structures
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2003
- ESSCIRC 2003
A Pico-Joule Class, 1 GHz, 32 KByte × 64b DSP SRAM with Self Reverse Bias
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2003
- VLSI Circuits 2003
Understanding and minimizing ground bounce during mode transition of power gating structures
- S. Kim
- S.V. Kosonocky
- et al.
- 2003
- ISLPED 2003