High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Publications
Date
Featured collections
Popular topics
27 results for Laertis Economikos
Cu CMP and its challenge for 20nm nodes and beyond
- John H. Zhang
- Wei-Tsu Tseng
- et al.
- 2012
- MRS Spring Meeting 2012
Optimizing stressor film deposition sequence in polish rate order for best planarization
- John H. Zhang
- Changyong Xiao
- et al.
- 2011
- MRS Spring Meeting 2011
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Hybrid clean approach for post-copper CMP defect reduction
- Wei-Tsu Tseng
- Vamsi Devarapalli
- et al.
- 2013
- ASMC 2013
Improvements in profile control using ISPC™ system during the stop-in-oxide CMP step in the RMG process flow on IBM 20nm short-loop wafers
- P. Komarenko
- J. Qian
- et al.
- 2012
- ICPT 2012
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes
- Wei-Tsu Tseng
- Donald Canaperi
- et al.
- 2012
- ASMC 2012
Using CMP model for 45nm/32nm BEOL process and design evaluations
- Laertis Economikos
- Jerry Bao
- et al.
- 2010
- ECS Meeting 2010