Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies
- M. Bhuiyan
- M. Kim
- et al.
- 2021
- IEDM 2021
Publications
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22 results for Kai Zhao
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- R. Bao
- C. Durfee
- et al.
- 2021
- IEDM 2021
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges
- F. Chen
- Carole Graas
- et al.
- 2015
- Microelectronics Reliability
A critical analysis of sampling-based reconstruction methodology for dielectric breakdown systems (BEOL/MOL/FEOL)
- Ernest Y. Wu
- James Stathis
- et al.
- 2015
- IRPS 2015
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015