CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond
- Takashi Ando
- Eduard Cartier
- et al.
- 2016
- IEDM 2016
Publications
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40 results for Sivananda Kanakasabapathy
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
- Q. Liu
- M. Vinet
- et al.
- 2013
- IEDM 2013
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- Zhibin Ren
- S. Mehta
- et al.
- 2011
- IEDM 2011
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- IEDM 2009
Demonstration of highly scaled FinFET SRAM cells with high-Κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
- H. Kawasaki
- M. Khater
- et al.
- 2008
- IEDM 2008
A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)
- R. Beach
- T. Min
- et al.
- 2008
- IEDM 2008