Spacer defined double patterning for sub-72 nm pitch logic technology
- Ryoung-Han Kim
- Erin McLellan
- et al.
- 2010
- SPIE Advanced Lithography 2010
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40 results for Sivananda Kanakasabapathy
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- VLSI Technology 2009
Overcoming the challenges of 22-nm node patterning through litho-design co-optimization
- Martin Burkharde
- J.C. Arnold
- et al.
- 2009
- SPIE Advanced Lithography 2009
Recent advances in MRAM technology
- W.J. Gallagher
- D.W. Abraham
- et al.
- 2005
- VLSI Technology 2005
A 0.18μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications
- A.R. Sitaram
- D.W. Abraham
- et al.
- 2003
- VLSI Technology 2003
Nitride etching with hydrofluorocarbons III: Comparison of C4H9F and CH3F for low-k′ nitride spacer etch processes
- Hiroyuki Miyazoe
- Nathan Marchack
- et al.
- 2018
- JVSTB
Development of TiO2 containing hardmasks through plasma-enhanced atomic layer deposition
- Anuja De Silva
- Indira Seshadri
- et al.
- 2017
- J. Micro/Nanolithogr. MEMS MOEMS
Fabrication and characterization of MgO-based magnetic tunnel junctions for spin momentum transfer switching
- Solomon Assefa
- J. Nowak
- et al.
- 2007
- Journal of Applied Physics
Materials and devices for reduced switching field toggle magnetic random access memory
- D.C. Worledge
- P.L. Trouilloud
- et al.
- 2006
- Journal of Applied Physics
Two-level BEOL processing for rapid iteration in MRAM development
- Michael C. Gaidis
- Eugene J. O'Sullivan
- et al.
- 2006
- IBM J. Res. Dev