A stochastic model for impact of LER on BEOL TDDB
- Ramachandran Muralidhar
- Ernest Y. Wu
- et al.
- 2017
- IRPS 2017
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169 results for Jim Stathis
A new and holistic modelling approach for impact of line-edge roughness on dielectric reliability
- Ernest Y. Wu
- Ramachandran Muralidhar
- et al.
- 2017
- IRPS 2017
Comparison of DC and AC NBTI kinetics in RMG Si and SiGe p-FinFETs
- Narendra Parihar
- Richard G. Southwick
- et al.
- 2017
- IRPS 2017
Fundamental statistical properties of reconstruction methodology for TDDB with variability in BEOL/MOL/FEOL applications
- Ernest Y. Wu
- James Stathis
- et al.
- 2016
- IRPS 2016
Process optimizations for NBTI/PBTI for future replacement metal gate technologies
- Barry P. Linder
- A. Dasgupta
- et al.
- 2016
- IRPS 2016
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
- Tenko Yamashita
- S. Mehta
- et al.
- 2015
- VLSI Technology 2015
Low-κ and High-κ breakdown statistics with variability: Clustering model versus reconstruction methodology (Invited)
- Ernest Y. Wu
- Baozhen Li
- et al.
- 2015
- IPFA 2015
Separation of interface states and electron trapping for hot carrier degradation in ultra-scaled replacement metal gate n-FinFET
- Miaomiao Wang
- Zuoguang Liu
- et al.
- 2015
- IRPS 2015
Analyzing path delays for accelerated testing of logic chips
- Emily Ray
- Barry P. Linder
- et al.
- 2015
- IRPS 2015