Hot carrier effect in ultra-scaled replacement metal gate Sii-xGex channel p-FinFETs
- Miaomiao Wang
- X. Miao
- et al.
- 2016
- IEDM 2016
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96 results for Barry P. Linder
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Reliability challenges for the 10nm node and beyond
- 2014
- IEDM 2014
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Fundamental aspects of HfO 2-based high-k metal gate stack reliability and implications on t inv-scaling
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- IEDM 2011
Impact of TDDB in MG/HK devices on circuit functionality in advanced CMOS technologies
- Andreas Kerber
- D. Lipp
- et al.
- 2011
- IEDM 2011
Fundamental understanding and optimization of PBTI in nFETs with SiO 2/HfO2 gate stack
- E. Cartier
- B.P. Linder
- et al.
- 2006
- IEDM 2006
A comparison of electrical and physical properties of MOCVD hafnium silicate thin films deposited using various silicon precursors
- P. Jamison
- M. Copel
- et al.
- 2006
- MRS Spring Meeting 2006
Systematic study of workfunction engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks
- Y.-H. Kim
- C. Cabral Jr.
- et al.
- 2005
- IEDM 2005
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- E. Gusev
- C. Cabral Jr.
- et al.
- 2004
- IEDM 2004