Combined ramp voltage stress and constant voltage stress for optimal BTI voltage acceleration and lifetime modeling
- Barry P. Linder
- Takashi Ando
- 2014
- IRPS 2014
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96 results for Barry P. Linder
Metal Gate/High-κ dielectric gate stack reliability; or how i learned to live with trappy oxides
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- ECS Meeting 2013
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
Improving and optimizing reliability in future technologies with high-κ dielectrics
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- VLSI-DAT 2013
Improving and optimizing reliability in future technologies with high-κ dielectrics
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- VLSI-TSA 2013
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013
Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- Siddarth Krishnan
- Vijay Narayanan
- et al.
- 2012
- IRPS 2012
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Separating NBTI and PBTI effects on the degradation of ring oscillator frequency
- Barry P. Linder
- Jae-Joon Kim
- et al.
- 2011
- IIRW 2011
Voltage ramp stress based stress-and-sense test method for reliability characterization of Hf-base high-k/metal gate stacks for CMOS technologies
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- ECS Meeting 2011