Interaction Between ti and SiO2
- C.-Y. Ting
- M. Wittmer
- et al.
- 2019
- JES
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124 results for Subramanian S. Iyer
Lowerature wafer bonding for three-dimensional wafer-scale integration
- Zhe Wan
- Kevin Winstel
- et al.
- 2018
- S3S 2018
Toward human-scale brain computing using 3D wafer scale integration
- Arvind Kumar
- Zhe Wan
- et al.
- 2017
- ACM JETC
Vertical channel devices enabled by through silicon via (TSV) technologies
- C. Kothandaraman
- Sami Rosenblatt
- et al.
- 2016
- IEDM 2016
Charge Trap Transistor (CTT): An embedded fully logic-compatible multiple-time programmable non-volatile memory element for high-k-metal-gate CMOS technologies
- Faraz Khan
- Eduard Cartier
- et al.
- 2017
- IEEE Electron Device Letters
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- Toshiaki Kirihata
- John Golz
- et al.
- 2016
- IEEE JESTCS
3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS
- J. Safran
- Giri N. K. Rangan
- et al.
- 2016
- ECTC 2016
The Impact of Self-Heating on Charge Trapping in High-k-Metal-Gate nFETs
- Faraz Khan
- Eduard Cartier
- et al.
- 2016
- IEEE Electron Device Letters
An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates
- Katsuyuki Sakuma
- Krishna Tunga
- et al.
- 2015
- ECTC 2015
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
- C. Kothandaraman
- X. Chen
- et al.
- 2015
- IRPS 2015