Copper through silicon via (TSV) for 3D integration
C. Kothandaraman, B. Himmel, et al.
IRPS 2012
This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking and high density cache memory, with operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 . The paper concludes with comments on the challenges for future 3D DRAMs.
C. Kothandaraman, B. Himmel, et al.
IRPS 2012
Yohji Watanabe, Hing Wong, et al.
IEICE Transactions on Electronics
Wei Lin, Juntao Li, et al.
LTB-3D 2014
Toshiaki Kirihata
LTB-3D 2014