Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
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15 results for Walter Kleemeier
External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology
- Oleg Gluschenkov
- Heng Wu
- et al.
- 2018
- IEDM 2018
Leakage aware Si/SiGe CMOS FinFET for low power applications
- G. Tsutsui
- C. Durfee
- et al.
- 2018
- VLSI Technology 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
CMP Challenges for Advanced Technology Nodes
- John H Zhang
- Haigou Huang
- et al.
- 2017
- MRS Advances
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
10nm FINFET technology for low power and high performance applications
- D. Guo
- H. Shang
- et al.
- 2014
- ICSICT 2014
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
- Q. Liu
- M. Vinet
- et al.
- 2013
- IEDM 2013
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012