Resistivity of copper interconnects beyond the 7 nm node
- Adam Pyzyna
- Robert L. Bruce
- et al.
- 2015
- VLSI Technology 2015
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21 results for M. Lofaro
An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch
- V. Djara
- Veeresh Deshpande
- et al.
- 2015
- VLSI Technology 2015
Post Porosity Plasma Protection applied to a wide range of ultra low-k materials
- Theo Frot
- Willi Volksen
- et al.
- 2012
- IITC 2012
Large-scale (512kbit) integration of multilayer-ready access-devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield
- G.W. Burr
- K. Virwani
- et al.
- 2012
- VLSI Technology 2012
Post Porosity Plasma Protection a new approach to integrate k 2.2 porous ULK materials
- Theo Frot
- Willi Volksen
- et al.
- 2011
- IITC/MAM 2011
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008
BEOL interconnects for 45 nm node and beyond
- R.R. Yu
- J. Doyle
- et al.
- 2005
- VMIC 2005
Integrated nanoscale deterministic lateral displacement arrays for separation of extracellular vesicles from clinically-relevant volumes of biological samples
- Joshua T. Smith
- Benjamin Wunsch
- et al.
- 2018
- Lab on a Chip
Towards large size substrates for III-V co-integration made by direct wafer bonding on Si
- Nicolas Daix
- Emanuele Uccelli
- et al.
- 2014
- APL Materials
BEOL Cu CMP process evaluation for advanced technology nodes
- Kunaljeet Tanwar
- Donald Canaperi
- et al.
- 2013
- JES