Towards large size substrates for III-V co-integration made by direct wafer bonding on Si
- Nicolas Daix
- Emanuele Uccelli
- et al.
- 2014
- APL Materials
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21 results for M. Lofaro
BEOL Cu CMP process evaluation for advanced technology nodes
- Kunaljeet Tanwar
- Donald Canaperi
- et al.
- 2013
- JES
200 mm wafer-scale integration of sub-20 nm sacrificial nanofluidic channels for manipulating and imaging single DNA molecules
- C. Wang
- S.W. Nam
- et al.
- 2013
- IEDM 2013
Ultra low contact resistivities for CMOS beyond 10-nm node
- Zhen Zhang
- Siyuranga Obasa Koswatta
- et al.
- 2013
- IEEE Electron Device Letters
Cu CMP and its challenge for 20nm nodes and beyond
- John H. Zhang
- Wei-Tsu Tseng
- et al.
- 2012
- MRS Spring Meeting 2012
Post Porosity Plasma Protection applied to a wide range of ultra low-k materials
- Theo Frot
- Willi Volksen
- et al.
- 2012
- IITC 2012
Large-scale (512kbit) integration of multilayer-ready access-devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield
- G.W. Burr
- K. Virwani
- et al.
- 2012
- VLSI Technology 2012
Integration of a manufacturing grade, k = 2.0 spin-on material in a single damascene structure
- Willi Volksen
- Sampath Purushothaman
- et al.
- 2012
- ECS J. Solid State Sci. Technol.
Post Porosity Plasma Protection a new approach to integrate k 2.2 porous ULK materials
- Theo Frot
- Willi Volksen
- et al.
- 2011
- IITC/MAM 2011
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008