A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
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38 results for Sergey V. Rylov
Static bipolar 11 GHz SiGe divider with 1V power supply
- Sergey Rylov
- Alexander Rylyakov
- 2003
- BCTM 2003
A 30Gb/s 1:4 demultiplexer in 0.12μm CMOS
- Alexander Rylyakov
- Sergey Rylov
- et al.
- 2003
- ISSCC 2003
An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz
- Montek Singh
- Jose A. Tierno
- et al.
- 2002
- ASYNC 2002
A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference
A 2.3GSample/s 10-tap digital FIR filter for magnetic recording read channels
- S. Rylov
- A. Rylyakov
- et al.
- 2001
- ISSCC 2001