The impact of aging effects and manufacturing variation on SRAM soft-error rate
- Ethan H. Cannon
- A.J. KleinOsowski
- et al.
- 2008
- IEEE T-DMR
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199 results for Rajiv V. Joshi
Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation
- Rouwaida Kanj
- Rajiv V. Joshi
- et al.
- 2008
- IEEE Trans Semicond Manuf
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- Microelectronics Journal
Leakage power analysis of 25-nm double-gate CMOS devices and circuits
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2005
- IEEE Transactions on Electron Devices
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2004
- Solid-State Electronics
Scaling planar silicon devices
- Ching-Te Chuang
- Kerry Bernstein
- et al.
- 2004
- IEEE Circuits and Devices Magazine
Turning silicon on its edge
- Edward J. Nowak
- Ingo Aller
- et al.
- 2004
- IEEE Circuits and Devices Magazine
Power analysis of strained-Si devices/circuits
- Keunwoo Kim
- Rajiv V. Joshi
- et al.
- 2004
- Solid-State Electronics
PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
Modeling 3D effects of substrate topography on step coverage and film morphology of thin metal films
- T. Smy
- S.K. Dew
- et al.
- 2002
- Thin Solid Films