High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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45 results for Rama Divakaruni
Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
New layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Effect of germanium preamorphization implant on performance and gate-induced drain leakage in SiGe channel pFET
- Vishal A. Tiwari
- Young Way Teh
- et al.
- 2015
- IEEE Electron Device Letters
Blanket SMT with in situ N2 plasma treatment on the lang;100〉 wafer for the low-cost low-power technology application
- Jun Yuan
- Victor Chan
- et al.
- 2009
- IEEE Electron Device Letters
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
- J. Beintner
- Y. Li
- et al.
- 2004
- IEEE Electron Device Letters
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Challenges of 10 nm and 7 nm CMOS for server and mobile applications
- Rama Divakaruni
- Vijay Narayanan
- 2016
- ECS Meeting 2016