Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
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62 results for Dechao Guo
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Advanced Arsenic Doped Epitaxial Growth for Source Drain Extension Formation in Scaled FinFET Devices
- Shogo Mochizuki
- B. Colombeau
- et al.
- 2018
- IEDM 2018
External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology
- Oleg Gluschenkov
- Heng Wu
- et al.
- 2018
- IEDM 2018
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si
- Choonghyun Lee
- Richard G. Southwick
- et al.
- 2018
- IEDM 2018
Extendable and Manufacturable Volume-less Multi-Vt Solution for 7nm Technology Node and beyond
- Ruqiang Bao
- Huimei Zhou
- et al.
- 2018
- IEDM 2018
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
A comparative study of strain and Ge content in Si1-xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs
- Choonghyun Lee
- Shogo Mochizuki
- et al.
- 2017
- IEDM 2017
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017