Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures
- Zuoguang Liu
- Heng Wu
- et al.
- 2019
- VLSI Technology 2019
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62 results for Dechao Guo
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
- Miaomiao Wang
- Jingyun Zhang
- et al.
- 2019
- IRPS 2019
Failure isolation in ring oscillator circuit and defect detection in CMOS technology research
- Victor Chan
- M. Bergendahl
- et al.
- 2019
- ASMC 2019
Leakage aware Si/SiGe CMOS FinFET for low power applications
- G. Tsutsui
- C. Durfee
- et al.
- 2018
- VLSI Technology 2018
Differentiated performance and reliability enabled by multi-work function solution in RMG Silicon and SiGe MOSFETs
- Ruqiang Bao
- Richard G. Southwick
- et al.
- 2018
- VLSI Technology 2018
Ring oscillator yield learning methodologies for CMOS technology research
- Victor Chan
- D. Lea
- et al.
- 2018
- ASMC 2018
SiGe FinFET for practical logic libraries by mitigating local layout effect
- G. Tsutsui
- Huimei Zhou
- et al.
- 2017
- VLSI Technology 2017
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016