Publications

53 results for Pouya Hashemi

Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs
- - Guohan Hu
  - M. G. Gottwald
  - et al.
- 2017
- IEDM 2017
High performance and reliable strained SiGe PMOS FinFETs enabled by advanced gate stack engineering
- - Pouya Hashemi
  - Takashi Ando
  - et al.
- 2017
- IEDM 2017
Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially Grown Emitter/Collector Regions
- - Pouya Hashemi
  - Jeng-Bang Yau
  - et al.
- 2017
- IEEE J-EDS
High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process
- - Pouya Hashemi
  - Takashi Ando
  - et al.
- 2017
- VLSI Technology 2017
High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length
- - Xiao Sun
  - Christopher P. D’Emic
  - et al.
- 2017
- VLSI Technology 2017
High performance PMOS with strained high-Ge-content SiGe fins for advanced logic applications
- - Pouya Hashemi
  - Takashi Ando
  - et al.
- 2017
- VLSI-TSA 2017
Three-dimensional monolithic integration of III-V and Si(Ge) FETs for hybrid CMOS and beyond
- - Veeresh Deshpande
  - Vladimir Djara
  - et al.
- 2017
- Japanese Journal of Applied Physics
High Mobility High-Ge-Content SiGe PMOSFETs Using Al₂O₃/HfO₂ Stacks with In-Situ O₃ Treatment
- - Takashi Ando
  - Pouya Hashemi
  - et al.
- 2017
- IEEE Electron Device Letters
DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration
- - Veeresh Deshpande
  - V. Djara
  - et al.
- 2017
- Solid-State Electronics
Prospects of high-Ge-content strained SiGe for advanced FinFET generations
- - Pouya Hashemi
  - Karthik Balakrishnan
  - et al.
- 2016
- PRiME/ECS Meeting 2016