A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
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70 results for Daniel Worledge
First demonstration of high retention energy barriers and 2 ns switching, using magnetic ordered-alloy-based STT MRAM devices
- Matthias Gottwald
- Guohan Hu
- et al.
- 2024
- VLSI Technology and Circuits 2024
Double spin-torque magnetic tunnel junction devices for last-level cache applications
- G. Hu
- C. Safranski
- et al.
- 2022
- IEDM 2022
Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions
- C. Safranski
- G. Hu
- et al.
- 2022
- VLSI Technology and Circuits 2022
2X reduction of STT-MRAM switching current using double spin-torque magnetic tunnel junction
- Guohan Hu
- Jonathan Sun
- et al.
- 2021
- IEDM 2021
First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications
- H. Wu
- V. Katragadda
- et al.
- 2021
- IEDM 2021
Demonstration of narrow switching distributions in STT-MRAM arrays for LLC applications at 1x nm node
- E. R.J. Edwards
- Guohan Hu
- et al.
- 2020
- IEDM 2020
Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications
- Guohan Hu
- D. Kim
- et al.
- 2019
- IEDM 2019
Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs
- Guohan Hu
- M. G. Gottwald
- et al.
- 2017
- IEDM 2017
STT-MRAM with double magnetic tunnel junctions
- Guohan Hu
- J.H. Lee
- et al.
- 2015
- IEDM 2015