A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Publications
Date
Featured collections
Popular topics
59 results for Hemanth Jagannathan
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
D2W and W2W Hybrid bonding system with below 2.5 micron pitch for 3D chiplet AI applications
- Katsuyuki Sakuma
- Roy Yu
- et al.
- 2024
- IEDM 2024
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022
Superior PBTI reliability for SOI FinFET technologies and its physical understanding
- Miaomiao Wang
- Ramachandran Muralidhar
- et al.
- 2013
- IEEE Electron Device Letters
Mechanism for leakage reduction by la incorporation in a HfO 2SiO2Si gate stack
- Kenzo Manabe
- Koji Watanabe
- et al.
- 2013
- IEEE Electron Device Letters
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- Kingsuk Maitra
- Ali Khakifirooz
- et al.
- 2011
- IEEE Electron Device Letters
Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect
- Sujata Paul
- Frank Yeh
- et al.
- 2010
- IEEE Electron Device Letters
Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023