Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
- H.-S. Wong
- David J. Franks
- et al.
- 1998
- IEDM 1998
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114 results for H.-S. Philip Wong
Generalized scale length for two-dimensional effects in MOSFET's
- David J. Frank
- Yuan Taur
- et al.
- 1998
- IEEE Electron Device Letters
Digital imaging
- H.-S.Philip Wong
- J.P. Albert
- 1998
- IEEE Micro
Discrete random dopant distribution effects in nanometer-scale MOSFETs
- Hon-Sum Philip Wong
- Yuan Taur
- et al.
- 1998
- Microelectronics Reliability
Fabrication of ultrathin, highly uniform thin-film soi mosfet's with low series resistance using pattern-constrained epitaxy
- Hon-Sum Wong
- 1997
- IEEE Transactions on Electron Devices
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
- H.-S. Wong
- K.K. Chan
- et al.
- 1997
- IEDM 1997
CMOS image sensors - recent advances and device scaling considerations
- H.-S. Wong
- 1997
- IEDM 1997
CMOS scaling into the nanometer regime
- Yuan Taur
- Douglas A. Buchanan
- et al.
- 1997
- Proceedings of the IEEE
Technology and device scaling considerations for CMOS imagers
- Hon-Sum Wong
- 1996
- IEEE Transactions on Electron Devices
Ultra-thin, highly uniform thin film SOI MOSFET with low series resistance using pattern-constrained epitaxy (PACE)
- H.-S. Wong
- K.K. Chan
- et al.
- 1996
- VLSI Technology 1996