Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization
- N. Gong
- Malte J. Rasch
- et al.
- 2022
- IEDM 2022
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32 results for Soon-Cheon Seo
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- IEDM 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters
Evaluation of direct cu electroplating on Ru: Feature fill, parametric, and reliability
- C.-C. Yang
- B. Li
- et al.
- 2011
- IEEE Electron Device Letters
Hardware Algorithm Co-optimization on Resistive RAM Cross-bar Array for Scalable Analog Compute Technology for AI application
- Y. Kim
- S.-C. Seo
- et al.
- 2021
- SNW 2021
Process-Induced ReRAM Performance Improvement of Atomic Layer Deposited HfO2 for Analog In-Memory Computing Applications
- Steven Consiglio
- H. Higuchi
- et al.
- 2021
- IMCS 2021
Introduction to Analog Testing of Resistive Random Access Memory (RRAM) Devices towards Scalable Analog Compute Technology for Deep Learning
- Ruturaj Pujari
- Arthur Gasasira
- et al.
- 2021
- ASMC 2021