NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Publications
34 results for Soon-Cheon Seo
Reliable Cu Pillar Undercut Control Using the Endpoint Detection System
- Zachary Gardner
- Soon-Cheon Seo
- et al.
- 2024
- ASMC 2024
Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization
- N. Gong
- Malte J. Rasch
- et al.
- 2022
- IEDM 2022
Hardware Algorithm Co-optimization on Resistive RAM Cross-bar Array for Scalable Analog Compute Technology for AI application
- Y. Kim
- S.-C. Seo
- et al.
- 2021
- SNW 2021
Process-Induced ReRAM Performance Improvement of Atomic Layer Deposited HfO2 for Analog In-Memory Computing Applications
- Steven Consiglio
- H. Higuchi
- et al.
- 2021
- IMCS 2021
Introduction to Analog Testing of Resistive Random Access Memory (RRAM) Devices towards Scalable Analog Compute Technology for Deep Learning
- Ruturaj Pujari
- Arthur Gasasira
- et al.
- 2021
- ASMC 2021
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016