65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
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11 results for Fen Jamin
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
Issues in NiSi-gated FDSOI device integration
- Jakub Kedzierski
- Diane Boyd
- et al.
- 2003
- IEDM 2003
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Extreme scaling with ultra-thin Si channel MOSFETs
- Bruce Doris
- Meikei Ieong
- et al.
- 2002
- IEDM 2002
Monolithically integrated silicon nitride platform
- Yusheng Bian
- Colleen Meagher
- et al.
- 2021
- OFC 2021
Monolithically integrated silicon nitride platform
- Yusheng Bian
- Colleen Meagher
- et al.
- 2021
- OFC 2021
Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005