Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
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13 results for Craig Child
Strategy of Insertion of Merge Features in a Sea of Wires SADP Integration
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2018
- IITC 2018
Segment removal strategy in SAQP for advanced BEOL application
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2017
- IITC 2017
Planarity considerations in SADP for advanced BEOL patterning
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2017
- IITC 2017
Optimization of porous ultra low- dielectrics (κ≤ 2.55) for 28nm generation
- D. Kioussis
- E.T. Ryan
- et al.
- 2011
- IITC/MAM 2011
Competitive and cost effective copper/low-k interconnect (BEOL) for 28nm CMOS technologies
- Rod Augur
- Craig Child
- et al.
- 2010
- ADMETA 2010
CoWP metal caps for reliable 32 nm 1X Cu interconnects in porous ULK (k=2.4)
- E. Huang
- M. Oh
- et al.
- 2009
- ADMETA 2009
UV curing-induced photoresist poisoning in advanced ULK BEOL integration schemes
- Y.C. Ee
- D. Kioussis
- et al.
- 2009
- ADMETA 2009
Effect of TaN stoichiometry on barrier oxidation and defect density in 32nm Cu/ultra-low K interconnects
- Andrew H. Simon
- Frieder Baumann
- et al.
- 2010
- MRS Online Proceedings Library
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009