Atomic layer deposition of sidewall spacers: Process, equipment and integration challenges in state-of-the-art logic technologies
- Michael Belyansky
- Richard Conti
- et al.
- 2014
- ECS Meeting 2014
Publications
25 results for Michael Belyansky
Characterization and mitigation of overlay error on silicon wafers with nonuniform stress
- T.A. Brunner
- V. Menon
- et al.
- 2014
- SPIE Advanced Lithography 2014
Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress
- Timothy A. Brunner
- Vinayan C. Menon
- et al.
- 2013
- Journal of Micro/Nanolithography, MEMS, and MOEMS
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010
Stress liner effects for 32-nm SOI MOSFETs with HKMG
- Ming Cai
- Karthik Ramani
- et al.
- 2010
- IEEE T-ED
Study of silicon strain in shallow trench isolation
- M. Belyansky
- N. Klymko
- et al.
- 2010
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Blanket SMT with in situ N2 plasma treatment on the lang;100〉 wafer for the low-cost low-power technology application
- Jun Yuan
- Victor Chan
- et al.
- 2009
- IEEE Electron Device Letters
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- M. Cai
- B. Greene
- et al.
- 2008
- IEEE International SOI Conference 2008