Ruilong Xie, Chanro Park, et al.
VLSI Technology 2019
Strain effects from stress liners on silicon-on-insulator MOSFETs with high- k dielectric and metal gate (HKMG) are reported. By thoroughly evaluating their impact on drive current, mobility, and threshold voltage, the intrinsic performance gain of stress liners is quantified at the 32-nm node with mobility enhancement identified as the major source. It is also experimentally demonstrated that advantageous stress liners can reduce gate leakage currents for MOSFETs with HKMG. © 2006 IEEE.
Ruilong Xie, Chanro Park, et al.
VLSI Technology 2019
Manjul Bhushan, Mark B. Ketchen, et al.
IEEE Trans Semicond Manuf
Katsuyuki Sakuma, Roy Yu, et al.
ECTC 2022
Qianwen Chen, Michael Belyansky, et al.
ECTC 2023