Scalability and biasing strategy for CMOS with active well bias
- S. Huang
- C. Wann
- et al.
- 2001
- VLSI Technology 2001
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80 results for Robert Dennard
Design guidelines for short, medium, and long on-chip interconnections
- A. Deutsch
- W.D. Becker
- et al.
- 1996
- IEEE Topical Meeting EPEPS 1996
Floating-body concerns for SOI dynamic random access memory (DRAM)
- J.A. Mandelman
- J. Barth
- et al.
- 1996
- IEEE International SOI Conference 1996
Iddq test: Sensitivity analysis of scaling
- T.W. Williams
- R.H. Dennard
- et al.
- 1996
- IEEE ITC 1996
Accurate measurement of pass-transistor leakage current in SOI MOSFETs
- F. Assaderaghi
- G. Shahidi
- et al.
- 1996
- IEEE International SOI Conference 1996
History dependence of non-fully depleted (NFD) digital SOI circuits
- F. Assaderaghi
- G. Shahidi
- et al.
- 1996
- VLSI Technology 1996
Iddq testing for high performance CMOS - The next ten years
- T.W. Williams
- R. Kapur
- et al.
- 1996
- EDTC 1996
Iddq testing for high performance CMOS - the next ten years
- T.W. Williams
- R. Kapur
- et al.
- 1996
- EDTC 1996
CMOS technology for low voltage/low power applications
- B. Davari
- R.H. Dennard
- et al.
- 1994
- CICC 1994
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993