Design of resonant global clock distributions
- Steven C. Chan
- Kenneth L. Shepard
- et al.
- 2003
- ICCD 2003
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66 results for Phillip Restle
Design and implementation of the POWER5™ microprocessor
- Joachim Clabes
- Joshua Friedrich
- et al.
- 2003
- ISSCC 2003
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
The clock distribution of the power4 microprocessor
- Phillip J. Restle
- Craig A. Carter
- et al.
- 2002
- ISSCC 2002
The circuit and physical design of the POWER4 microprocessor
- J. Warnock
- J. Keaty
- et al.
- 2002
- IBM J. Res. Dev
The clock distribution of the Power4 microprocessor
- Phillip J. Restle
- Craig A. Carter
- et al.
- 2002
- Digest of Technical Papers-IEEE International Solid-State Circuits Conference
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2002
- Proceedings of the Custom Integrated Circuits Conference
Technical visualizations in VLSI design
- P. Restle
- 2001
- DAC 2001
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
- Phillip J. Restle
- Albert E. Ruehli
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A clock distribution network for microprocessors
- Phillip J. Restle
- Timothy G. McNamara
- et al.
- 2001
- IEEE Journal of Solid-State Circuits