On-chip timing uncertainty measurements on IBM microprocessors
- R.L. Franch
- P. Restle
- et al.
- 2008
- IEEE ITC 2008
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66 results for Phillip Restle
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
- G.G. Lopez
- G. Fiorenza
- et al.
- 2005
- GLSVLSI 2005
New prospects for clocking synchronous and quasi-asynchronous systems
- Phillip Restle
- Ken Shepard
- 2005
- ASYNC 2005
Design and implementation of the POWER5™ microprocessor
- Joachim Clabes
- Joshua Friedrich
- et al.
- 2004
- ICICDT 2004
Design of resonant global clock distributions
- Steven C. Chan
- Kenneth L. Shepard
- et al.
- 2003
- ICCD 2003
Clock tree and power grid design > 1 GHz
- Phillip J. Restle
- Albert Ruehli
- et al.
- 2000
- ADMETA 2000
Designing the best clock distribution network
- P. Restle
- A. Deutsch
- 1998
- VLSI Circuits 1998
Importance of inductance and inductive coupling for on-chip wiring
- A. Deutsch
- H. Smith
- et al.
- 1997
- IEEE Topical Meeting EPEPS 1997
Design guidelines for short, medium, and long on-chip interconnections
- A. Deutsch
- W.D. Becker
- et al.
- 1996
- IEEE Topical Meeting EPEPS 1996
Submicron CMOS circuit simulation model accurate from liquid nitrogen to room temperature
- H.I. Hanafi
- T.J. Buccelot
- et al.
- 1989
- ESSDERC 1989