Vertical channel devices enabled by through silicon via (TSV) technologies
- C. Kothandaraman
- Sami Rosenblatt
- et al.
- 2016
- IEDM 2016
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10 results for Daniel Berger
3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS
- J. Safran
- Giri N. K. Rangan
- et al.
- 2016
- ECTC 2016
An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates
- Katsuyuki Sakuma
- Krishna Tunga
- et al.
- 2015
- ECTC 2015
Bonding technologies for chip level and wafer level 3D integration
- Katsuyuki Sakuma
- Spyridon Skordas
- et al.
- 2014
- ECTC 2014
3D copper TSV integration, testing and reliability
- Mukta Farooq
- T. Graves-Abe
- et al.
- 2011
- IEDM 2011
Three-dimensional chip stack with integrated decoupling capacitors and thru-si via interconnects
- Bing Dang
- Michael Shapiro
- et al.
- 2010
- IEEE Electron Device Letters
A CMOS Compatible Monolithic Fiber Attach Solution with Reliable Performance and Self-Alignment
- Bo Peng
- Tymon Barwicz
- et al.
- 2020
- OFC 2020
Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability
- Mukta Farooq
- Giuseppe La Rosa
- et al.
- 2015
- IRPS 2015
Reliable through silicon vias for 3D silicon applications
- M.J. Shapiro
- M. Interrante
- et al.
- 2009
- IITC 2009
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- Toshiaki Kirihata
- John Golz
- et al.
- 2016
- IEEE JESTCS