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In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nFmm2 is achieved with two-layer Si interposer chip stacks. © 2006 IEEE.
Kevin Tien, Noah Sturcken, et al.
VLSI Circuits 2015
Xiaoxiong Gu, Joel A. Silberman, et al.
IEEE Transactions on CPMT
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