Bing Dang, Paul Andry, et al.
ECTC 2010
In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nFmm2 is achieved with two-layer Si interposer chip stacks. © 2006 IEEE.
Bing Dang, Paul Andry, et al.
ECTC 2010
Bing Dang, Thomas Wassick, et al.
ECTC 2016
Paul Andry, Russell A. Budd, et al.
ECTC 2014
Bo Wen, Vince S. Siu, et al.
ICDH 2022