High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- B. Yang
- R. Takalkar
- et al.
- 2008
- IEDM 2008
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12 results for John Pellerin
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
- M. Horstmann
- A. Wei
- et al.
- 2005
- IEDM 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique
- James Pan
- Don Canaperi
- et al.
- 2004
- IEEE Electron Device Letters
Monolithically integrated silicon nitride platform
- Yusheng Bian
- Colleen Meagher
- et al.
- 2021
- OFC 2021
Monolithically integrated silicon nitride platform
- Yusheng Bian
- Colleen Meagher
- et al.
- 2021
- OFC 2021
A CMOS Compatible Monolithic Fiber Attach Solution with Reliable Performance and Self-Alignment
- Bo Peng
- Tymon Barwicz
- et al.
- 2020
- OFC 2020
Advanced metallization developments for 32-nm node CMOS technology contact architecture
- Doug H. Lee
- Valli Arunachalam
- et al.
- 2009
- ADMETA 2009
Implementation of robust nickel alloy salicide process for high-performance 65nm SOI CMOS manufacturing
- Jay Strane
- David Brown
- et al.
- 2007
- VLSI-TSA 2007