High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
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CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique
- James Pan
- Don Canaperi
- et al.
- 2004
- IEEE Electron Device Letters