Controlled-load limited switch dynamic logic circuit
- Jayakumaran Sivagnaname
- Hung C. Ngo
- et al.
- 2005
- ISQED 2005
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34 results for Robert Montoye
Testing and debugging delay faults in dynamic circuits
- Ramyanshu Datta
- Sani Nassif
- et al.
- 2005
- IEEE ITC 2005
A low latency and low power dynamic carry save adder
- Ramyanshu Datta
- Jacob A. Abraham
- et al.
- 2004
- ISCAS 2004
Value-based management of design reuse
- Juan Antonio Carballo
- David L. Cohn
- et al.
- 2003
- SPIE Advanced Microelectronic Manufacturing 2003
Ratioed CMOS: A low power high speed design choice in SOI technologies
- Christophe R. Tretz
- Robert K. Montoye
- et al.
- 2000
- IEEE International SOI Conference 2000
IBM second-generation RISC machine organization
- H.B. Bakoglu
- G.F. Grohoski
- et al.
- 1990
- COMPCON 1990
IBM second-generation RISC machine organization
- H.B. Bakoglu
- G.F. Grohoski
- et al.
- 1989
- ICCD 1989
DESIGN-PERFORMANCE TRADE-OFFS IN CMOS DOMINO LOGIC.
- Vojin G. Oklobdzija
- Robert K. Montoye
- 1984
- CICC 1984
Practical strategies for power-efficient computing technologies
- Leland Chang
- David J. Frank
- et al.
- 2010
- Proceedings of the IEEE
A 270ps 20mW 108-bit end-around carry adder for multiply-add fused floating point unit
- Xiao Yan Zhang
- Yiu-Hing Chan
- et al.
- 2009
- Journal of Signal Processing Systems