Limited switch dynamic logic circuits for high-speed low-power circuit design
- Wendy Belluomini
- Damir Jamsek
- et al.
- 2006
- IBM J. Res. Dev
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34 results for Robert Montoye
Controlled-load limited switch dynamic logic circuit
- Jayakumaran Sivagnaname
- Hung C. Ngo
- et al.
- 2005
- ISQED 2005
Testing and debugging delay faults in dynamic circuits
- Ramyanshu Datta
- Sani Nassif
- et al.
- 2005
- IEEE ITC 2005
Stable SRAM cell design for the 32 nm node and beyond
- Leland Chang
- David M. Fried
- et al.
- 2005
- VLSI Technology 2005
A low latency and low power dynamic carry save adder
- Ramyanshu Datta
- Jacob A. Abraham
- et al.
- 2004
- ISCAS 2004
Value-based management of design reuse
- Juan Antonio Carballo
- David L. Cohn
- et al.
- 2003
- SPIE Advanced Microelectronic Manufacturing 2003
A double precision floating point multiply
- Robert Montoye
- Wendy Belluomini
- et al.
- 2003
- ISSCC 2003
Ratioed CMOS: A low power high speed design choice in SOI technologies
- Christophe R. Tretz
- Robert K. Montoye
- et al.
- 2000
- IEEE International SOI Conference 2000
IBM second-generation RISC machine organization
- H.B. Bakoglu
- G.F. Grohoski
- et al.
- 1990
- COMPCON 1990
An 18 ns 56-bit multiply-adder circuit
- Robert K. Montoye
- P.W. Cook
- et al.
- 1990
- ISSCC 1990