A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
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74 results for Vamsi Paruchuri
Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes
- Takeshi Nogami
- Benjamin D. Briggs
- et al.
- 2015
- IEDM 2015
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Physical origin of pFET threshold voltage modulation by ge channel ion implantation (GC-I/I)
- Yoshinori Tsuchiya
- Nathaniel Berliner
- et al.
- 2010
- IEDM 2010
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Fundamental understanding and optimization of PBTI in nFETs with SiO 2/HfO2 gate stack
- E. Cartier
- B.P. Linder
- et al.
- 2006
- IEDM 2006
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- E. Gusev
- C. Cabral Jr.
- et al.
- 2004
- IEDM 2004
Charge trapping in aggressively scaled metal gate/high-κ stacks
- E. Gusev
- V. Narayanan
- et al.
- 2004
- IEDM 2004
Mechanism for leakage reduction by la incorporation in a HfO 2SiO2Si gate stack
- Kenzo Manabe
- Koji Watanabe
- et al.
- 2013
- IEEE Electron Device Letters