Next Generation Infrared (IR) Laser Debonding / Silicon Handle Technology for Precision Chiplet Technology Applications
- Qianwen Chen
- Michael Belyansky
- et al.
- 2023
- ECTC 2023
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12 results for S. Butt
Vertical channel devices enabled by through silicon via (TSV) technologies
- C. Kothandaraman
- Sami Rosenblatt
- et al.
- 2016
- IEDM 2016
3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS
- J. Safran
- Giri N. K. Rangan
- et al.
- 2016
- ECTC 2016
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Hardware-corroborated variability-aware SRAM methodology
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2013
- VLSID 2013
CMOS gate height scaling
- Zhibin Ren
- K. Schonenberg
- et al.
- 2008
- ICSICT 2008
Hole transport in nanoscale p-type MOSFET SOI devices with high strain
- H. Nayfeh
- S.-J. Jeng
- et al.
- 2007
- DRC 2007
Improving the power-performance of multicore processors through optimization of lithography and thermal processing
- A. Gabor
- T.A. Brunner
- et al.
- 2007
- SPIE Advanced Lithography 2007
Optimization of silicon technology for the IBM System z9
- Daniel J. Poindexter
- Scott R. Stiffler
- et al.
- 2007
- IBM J. Res. Dev