3-D silicon integration and silicon packaging technology using silicon through-vias
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
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28 results for Edmund Sprogis
Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ADMETA 2005
Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ECTC 2005
Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2005
- CICC 2005
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2005
- IBM J. Res. Dev
Buried-trench DRAM cell using a self-aligned epitaxy over trench technology
- N.C.-C. Lu
- T.V. Rajeevakumar
- et al.
- 1988
- IEDM 1988
A Substrate-Plate Trench-Capacitor (SPT) Memory Cell for Dynamic RAM's
- Nicky Chau-Chun Lu
- Tak H. Ning
- et al.
- 1986
- IEEE Journal of Solid-State Circuits
SPT CELL - A NEW SUBSTRATE - PLATE TRENCH CELL FOR DRAMS.
- N.C.-C. Lu
- P.E. Cottrell
- et al.
- 1984
- IEDM 1984