Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
- Sarunya Bangsaruntip
- K. Balakrishnan
- et al.
- 2013
- IEDM 2013
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22 results for Sarunya Bangsaruntip
Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs
- Amlan Majumdar
- Sarunya Bangsaruntip
- et al.
- 2012
- IEDM 2012
High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling
- S. Bangsaruntip
- G.M. Cohen
- et al.
- 2009
- IEDM 2009
Two-dimensional pattern formation using graphoepitaxy of PS-b-PMMA block copolymers for advanced FinFET device and circuit fabrication
- Hsinyu Tsai
- Jed W. Pitera
- et al.
- 2014
- ACS Nano
Universality of short-channel effects in undoped-body silicon nanowire MOSFETs
- Sarunya Bangsaruntip
- Guy M. Cohen
- et al.
- 2010
- IEEE Electron Device Letters
Low-temperature growth of strained germanium quantum wells for high mobility applications
- Stephen W. Bedell
- S. Hart
- et al.
- 2020
- PRiME 2020
Contact engineering and channel doping for robust carbon nanotube NFETs
- Jianshi Tang
- Damon B. Farmer
- et al.
- 2017
- VLSI-TSA 2017
Induced e-beam charge impact on spatial orientation of gate-All-Around silicon wires device fabricated on boron nitride substrate
- Shimon Levi
- Konstantin Chirko
- et al.
- 2015
- SPIE Advanced Lithography 2015
CD-SEM metrology evaluation of gate-all-around Si nanowire MOSFET with improved control of nanowire suspension by using a buried boron nitride etch-stop layer
- Guy M. Cohen
- Leathen Shi
- et al.
- 2014
- ASMC 2014
CDSEM AFM hybrid metrology for the characterization of gate-all-around silicon nano wires
- Shimon Levi
- Ishai Schwarzband
- et al.
- 2014
- SPIE Advanced Lithography 2014