Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
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17 results for Stuart Sieg
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
EUV sub-resolution assist feature impact: experimental and simulation evaluation
- Zheng Chen
- Martin Burkhardt
- et al.
- 2023
- OEN 2023
Focus considerations of design pitches and absorber choice for EUV random logic
- Martin Burkhardt
- Zheng Chen
- et al.
- 2022
- OEN 2022
EUVL mask process development and verification using advanced modeling and characterization techniques
- Michael Green
- Romain Lallement
- et al.
- 2020
- SPIE Advanced Lithography 2020
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
DSA patterning options for logics and memory applications
- Chi Chun Liu
- Elliott Franke
- et al.
- 2017
- SPIE Advanced Lithography 2017
An OCD perspective of line edge and line width roughness metrology
- Ravi Bonam
- R. Muthinti
- et al.
- 2017
- SPIE Advanced Lithography 2017
Comprehensive analysis of line-edge and line-width roughness for EUV lithography
- Ravi Bonam
- Chi Chun Liu
- et al.
- 2017
- SPIE Advanced Lithography 2017