EUVL mask process development and verification using advanced modeling and characterization techniques

Abstract

Mask technology is key to enabling the progression of advanced IC technology nodes into the realm beyond 7nm node logic. In particular, extreme ultraviolet lithography (EUVL) relies heavily on the mask in order to achieve adequate process window (PW) and final yields. In the EUVL environment, mask process development and verification becomes increasingly more difficult and costly. The mask manufacture costs are driven by multiple factors including significantly more expensive mask blanks and increased ebeam write times. Wafer verification of mask process improvements is very difficult with the relatively low number of early adopters of EUVL and high cost associated with processing non-product wafers with that technology. It is therefore useful for mask manufacturers and wafer lithographers to collaborate to develop low cost mask process screening techniques as a precursor to committing valuable EUV exposure time for final verification. Previously, we demonstrated that by utilizing a toolkit of mask and wafer analytical techniques known as advanced mask characterization and optimization (AMCO) [2], we were able to predict wafer defectivity on 1D and 2D metal structures and optimize a mask process to enable 30nm pitch interconnect in a single exposure step using EUVL [1]. In this study, we use similar methodology to develop a mask process for beyond 7nm node logic contact and via layers. These structures pose a different set of challenges than the metal layer. Contact hole area loss, corner rounding (CR), and mask process-induced x-y error on asymmetric holes must be optimized to deliver the required capability. Additionally, sub-resolution assist features (SRAFs) become relevant at this node. Resolving these on the mask is critical. Here, we describe the development of a mask process to overcome these challenges. We use advanced modeling techniques including AMCO to characterize the process improvements and predict wafer performance. Mask process improvements that are characterized include both physical mask process components as well as write data optimization techniques, i.e. mask process correction (MPC).