The projection of the incidence of dielectric cracking during chip joining with lead free solder bumps

Abstract

This study examines different approaches to determining the chip failure rate that occurs due to dielectric cracking under C4 sites during chip joining. We show that testing of the strength of individual C4s by a single bump shear technique gives a strength distribution that is well described by a Weibull distribution with a Weibull modulus that lies in the range 10-20. Simulations of the spatial distribution of failing C4s during a chip joining test using this distribution, however, are found to be inconsistent with those observed experimentally. From this observation we conclude that the observed fails arise from a defect population that is not well characterized by single bump shear tests. We propose an alternative to SBS testing in which we directly count the number of fails that occur at a given stress level by comparing the location of the fails observed in multiple sonoscan images of chips to the C4 stress map calculated from a finite element model. An example is presented where the strength distribution of the defect tail is characterized from the analysis of C4 fails induced by an accelerated chip joining test. From this distribution we show how it is possible to project chip failure rates that arise from a manufacturing chip joining process.