3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections
- Katsuyuki Sakuma
- Paul S. Andry
- et al.
- 2008
- IBM J. Res. Dev
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43 results for Robert Polastre
Three-dimensional silicon integration
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2008
- IBM J. Res. Dev
3D chip stacking with C4 technology
- Bing Dang
- Steven L. Wright
- et al.
- 2008
- IBM J. Res. Dev
A practical implementation of silicon microchannel coolers for high power chips
- Evan G. Colgan
- Bruce Furman
- et al.
- 2007
- IEEE Transactions on Components and Packaging Technologies
High performance and subambient silicon microchannel cooling
- E.G. Colgan
- B.K. Furman
- et al.
- 2006
- Journal of Heat Transfer
3-D silicon integration and silicon packaging technology using silicon through-vias
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
Silicon microchannel cooling for high power chips
- Evan G. Colgan
- Bruce Furman
- et al.
- 2006
- HVAC and R Research
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2005
- IBM J. Res. Dev
Thin-film-transistor process-characterization test structures
- E.G. Colgan
- R.J. Polastre
- et al.
- 1998
- IBM J. Res. Dev
A 10.5-in.-diagonal SXGA active-matrix display
- E.G. Colgan
- P.M. Alt
- et al.
- 1998
- IBM J. Res. Dev