A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS
- Alberto Valdes-Garcia
- Arun Natarajan
- et al.
- 2013
- RFIC 2013
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46 results for Benjamin D. Parker
A 73.9-83.5GHz synthesizer with -111dBc/Hz phase noise at 10MHz offset in a 130nm SiGe BiCMOS technology
- Jean-Olivier Plouchart
- Mark Ferriss
- et al.
- 2013
- RFIC 2013
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
- Jean-Olivier Plouchart
- Mihai Sanduleanu
- et al.
- 2012
- CICC 2012
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012
A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
- Sameh Asaad
- Ralph Bellofatto
- et al.
- 2012
- FPGA 2012
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
- Jae-Sun Seo
- Bernard Brezzo
- et al.
- 2011
- CICC 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011
A single-chip 12.5Gbaud transceiver for serial data communication
- D. Friedman
- M. Meghelli
- et al.
- 2001
- VLSI Circuits 2001